Optimization of NLDMOS Structure for Higher breakdown voltage and lower on-resistance

ASIA unversity > 管理學院 > 國際企業學系 > 期刊論文 > Item 310904400/79754

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://asiair.asia.edu.tw/ir/handle/310904400/79754

题名:	Optimization of NLDMOS Structure for Higher breakdown voltage and lower on-resistance
作者:	hema;hema;許健;Sheu, Gene;aryadeep;aryadeep;erry;erry;楊紹明;Yang, Shao-Ming;chen, PA;chen, PA
贡献者:	資訊工程學系
日期:	2014-05
上传时间:	2014-06-05 04:03:45 (UTC+0)
摘要:	In this work, high voltage NLDMOS performance in terms of high blocking voltage and On-Resistance have been investigated. In order to obtain the optimum electrical performance several key factors have been optimized such as linearity of HVNW profile, drift length and source field plate. Linear HVNW profile is obtained by linearity of HVNW mask. NLDMOS having blocking voltage of 100 V-300 V and lower On-resistance is developed based on 0.35um BCD Technology with less manufacturing cost. It is investigated that NLDMOS has poor performance over blocking voltage of 300V.
關聯:	2014 IEEE 8th International Power Engineering and Optimization Conference ;PEOCO2014), Langkawi, The Jewel of Kedah,
显示于类别:	[國際企業學系] 期刊論文

文件中的档案:

档案	大小	格式	浏览次数
index.html	0Kb	HTML	361	检视/开启

在ASIAIR中所有的数据项都受到原著作权保护.