Exceptions or interruptions control is the most challenging aspect while designing a processor, and the hardest work of exception control is interruption among produces. In this paper, we embedded an event controller (EC) into an RISC architecture processor to handle when interruption occurring, then to reduce the latency time when context switch between user program and kernel program. To analyze the performance, we also compare the cost/performance（C/P） ratio and the C/P improved ratio of the proposed processor in different entry number of a reorder buffers.
