ASIA unversity:Item 310904400/5786
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    题名: The Schema of Interrupt Controller
    作者: Jih-Fu Tu
    贡献者: St. John’s University
    关键词: Event controller (EC);cost/performance (C/P);external interrupt;and interrupt priority comparator
    日期: 2007-12-20
    上传时间: 2009-12-15
    出版者: 亞洲大學資訊學院;中華電腦學會
    摘要: Exceptions or interruptions control is the most challenging aspect while designing a processor, and the hardest work of exception control is interruption among produces. In this paper, we embedded an event controller (EC) into an RISC architecture processor to handle when interruption occurring, then to reduce the latency time when context switch between user program and kernel program. To analyze the performance, we also compare the cost/performance(C/P) ratio and the C/P improved ratio of the proposed processor in different entry number of a reorder buffers.
    關聯: 2007NCS全國計算機會議 12-20~21
    显示于类别:[資訊學院] 會議論文

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