In the modern architectures, if we want to increase the processor performance, we need to increase the ILP. TLP has been complemented to ILP in multithreaded architectures. In this paper, we present an evaluation of modern processor that decouples memory accesses to alleviate the gap, uses a non-blocking multithreaded together with the dataflow paradigm. We provide both clock cycles per instruction (CPI) and instructions per clock cycle (IPC) evaluation of a multithreaded architecture by using speculative execution. The existing architecture has been evaluated previously and shown that it has outperformed MIPS like architectures. In this particular study, we try to implement speculative execution of multithread on this unique architecture. Some of the benchmarks we used include I-structure that is unique to dataflow architecture and other benchmarks are without I-structure. All the benchmarks have shown speedup of about 1.3. In a speculative execution, it divides the thread aggressively and the mutual exclusion and dependence are guaranteed to be parallel. Thus it can increase the performance of any program with high probability. We have used different architectural simulators to prove the existing performance improvement of speculative execution.
