Speculative Execution of a Non-Blocking Multithreaded Architecture

ASIA unversity > 資訊學院 > 會議論文 > Item 310904400/5779

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://asiair.asia.edu.tw/ir/handle/310904400/5779

题名:	Speculative Execution of a Non-Blocking Multithreaded Architecture
作者:	Joseph M. Arul;Tsozen Yeh and HsuanYu Chen
贡献者:	Fu Jen Catholic University
日期:	2007-12-20
上传时间:	2009-12-15
出版者:	亞洲大學資訊學院;中華電腦學會
摘要:	In the modern architectures, if we want to increase the processor performance, we need to increase the ILP. TLP has been complemented to ILP in multithreaded architectures. In this paper, we present an evaluation of modern processor that decouples memory accesses to alleviate the gap, uses a non-blocking multithreaded together with the dataflow paradigm. We provide both clock cycles per instruction (CPI) and instructions per clock cycle (IPC) evaluation of a multithreaded architecture by using speculative execution. The existing architecture has been evaluated previously and shown that it has outperformed MIPS like architectures. In this particular study, we try to implement speculative execution of multithread on this unique architecture. Some of the benchmarks we used include I-structure that is unique to dataflow architecture and other benchmarks are without I-structure. All the benchmarks have shown speedup of about 1.3. In a speculative execution, it divides the thread aggressively and the mutual exclusion and dependence are guaranteed to be parallel. Thus it can increase the performance of any program with high probability. We have used different architectural simulators to prove the existing performance improvement of speculative execution.
關聯:	2007NCS全國計算機會議 12-20~21
显示于类别:	[資訊學院] 會議論文

文件中的档案:

档案	大小	格式	浏览次数
1022.pdf	237Kb	Adobe PDF	470	检视/开启

在ASIAIR中所有的数据项都受到原著作权保护.

数据加载中.....