In this paper, we will describe a block cipher algorithm called “twofish”[1]. Then a novel VLSI architecture of it will be presented. For the architecture of reused some core function, we can make it more efficient for encrypting and decrypting data-delivered. To verify our design theory and ensuring that it is workable to encrypt plaintext, we have implemented a prototype chip by using 0.35μ technology. By experimenting the chip while operating at 66MHz clock rate, we find that its throughput is 200Mbps and throughput per gate is about 5,700. Furthermore, it provides the function to execute encrypting and decrypting on network .The other features will be mentioned at following sections.
