VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER

ASIA unversity > 資訊學院 > 行動商務與多媒體應用學系 > 會議論文 > Item 310904400/5044

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://asiair.asia.edu.tw/ir/handle/310904400/5044

题名:	VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER
作者:	Li-Chung Chang;Yeong-Kang Lai;Liang-Gee Chen;Jian-Yi La;Tai-Ming Parng
贡献者:	Department of Electrical Engineering National Chung Hsing University;Department of Electrical Engineering,National Taiwan University
日期:	2002-05-16
上传时间:	2009-12-08 07:38:25 (UTC+0)
出版者:	亞洲大學
摘要:	In this paper, we will describe a block cipher algorithm called “twofish”[1]. Then a novel VLSI architecture of it will be presented. For the architecture of reused some core function, we can make it more efficient for encrypting and decrypting data-delivered. To verify our design theory and ensuring that it is workable to encrypt plaintext, we have implemented a prototype chip by using 0.35μ technology. By experimenting the chip while operating at 66MHz clock rate, we find that its throughput is 200Mbps and throughput per gate is about 5,700. Furthermore, it provides the function to execute encrypting and decrypting on network .The other features will be mentioned at following sections.
關聯:	第十二屆全國資訊安全會議 277-284
显示于类别:	[行動商務與多媒體應用學系] 會議論文

文件中的档案:

档案	描述	大小	格式	浏览次数
310904400-5044.doc		38Kb	Microsoft Word	202	检视/开启

在ASIAIR中所有的数据项都受到原著作权保护.