VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER

ASIAIR > College of Computer Science > Department of Applied Informatics and Multimedia > Proceedings > Item 310904400/5044

Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/5044

Title:	VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER
Authors:	Li-Chung Chang;Yeong-Kang Lai;Liang-Gee Chen;Jian-Yi La;Tai-Ming Parng
Contributors:	Department of Electrical Engineering National Chung Hsing University;Department of Electrical Engineering,National Taiwan University
Date:	2002-05-16
Issue Date:	2009-12-08 07:38:25 (UTC+0)
Publisher:	亞洲大學
Abstract:	In this paper, we will describe a block cipher algorithm called “twofish”[1]. Then a novel VLSI architecture of it will be presented. For the architecture of reused some core function, we can make it more efficient for encrypting and decrypting data-delivered. To verify our design theory and ensuring that it is workable to encrypt plaintext, we have implemented a prototype chip by using 0.35μ technology. By experimenting the chip while operating at 66MHz clock rate, we find that its throughput is 200Mbps and throughput per gate is about 5,700. Furthermore, it provides the function to execute encrypting and decrypting on network .The other features will be mentioned at following sections.
Relation:	第十二屆全國資訊安全會議 277-284
Appears in Collections:	[Department of Applied Informatics and Multimedia] Proceedings

Files in This Item:

File	Description	Size	Format
310904400-5044.doc		38Kb	Microsoft Word	202	View/Open