ESD Simulation on GGNMOS for 40V BCD

ASIAIR > College of Computer Science > Department of Computer Science and Information Engineering > Journal Artical > Item 310904400/18675

Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/18675

Title:	ESD Simulation on GGNMOS for 40V BCD
Authors:	許健;Sheu, Gene;楊紹明;Yang, Shao-Ming
Contributors:	資訊工程學系
Keywords:	ESD, GGNMOS, TLP, BCD, Reliability
Date:	2010-10
Issue Date:	2012-11-26 05:56:54 (UTC+0)
Abstract:	In this paper, TCAD was used to simulate GGNMOS (Grounded-Gate NMOS) as an ESD protection device for 40V BCD. The physic models and the calibration method are discussed in order to get better accuracy on the result. The effects of device parameter on the ESD robustness are investigated by device simulation in order to achieve the desired ESD design window. The simulated holding voltage is in agreement with BJT model that already proven has an agreement with silicon result. Finally, the ESD design window for 40V BCD device can be obtained by changing some device parameters.
Relation:	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Appears in Collections:	[Department of Computer Science and Information Engineering] Journal Artical

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	344	View/Open