An enhanced dual-path ΔΣ analog-to-digital converter

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Title:	An enhanced dual-path ΔΣ analog-to-digital converter
Authors:	Nishida, Yoshio;Temes, Gabor C.
Contributors:	Department of Computer Science and Information Engineering
Keywords:	Analog to digital converters;CMOS processs;Delta-sigma ADC;Distortion ratio;Dual path;First-order;Input signal;Quantization noise;Signal bandwidth;Signal to noise;Switched capacitor circuits;Test chips
Date:	2009
Issue Date:	2010-04-08 12:21:58 (UTC+0)
Publisher:	Asia University
Abstract:	This paper presents an enhanced dual-path delta-sigma ADC. The first-order enhancement of the quantization noise shaping is achieved by employing a switched capacitor circuit technique. A test chip, fabricated in a 0.18-μm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75- dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2<sup>nd</sup> harmonic is -101-dB and the 3<sup>rd</sup> one is -94-dB when a -4.5-dB 100-kHz input signal is applied. ©2009 IEEE.
Relation:	Proceedings - IEEE International Symposium on Circuits and Systems :1333-1336
Appears in Collections:	[資訊工程學系] 會議論文

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