With the improvement of chip manufacture process, a single chip may contain many processor cores and functional units. These cores and functional units communicate with each other through an on-chip interconnection network. Therefore, a key issue in the design of multi-core chip is how to construct a low latency high bandwidth on-chip interconnect. In this paper, a cycle stealing buffer and a physical channel management scheme are proposed for the design of on chip networks. The cycle stealing buffer can reduce the number of cycles in reading and writing a network buffer. The physical channel management scheme can efficiently multiplex and arbitrate the physical channel among many virtual channels. These two methods can be adopted in wormhole based networks to improve both latency and throughput. In this paper, by use of simulation, we study the feasibility and benefits of these two methods using a wormhole based ring network.
