ASIA unversity:Item 310904400/12803
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    Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/12803


    Title: CV Measurement Simulation of Power Device for Different Structure
    Authors: Batsukh, Altansukh
    Contributors: Department of Computer Science and Information Engineering
    Yang, Shao Ming
    Keywords: LOCOS LDMOS;TAPERED LDMOS;ED-MOS;MOSFET
    Date: 2012
    Issue Date: 2012-11-18 09:53:55 (UTC+0)
    Publisher: Asia University
    Abstract: With the work reported in this manuscript we have essentially contributed to the electrical characterization and modelling of high voltage MOSFETs, more particularly LDMOS architectures such as LOCOS LDMOS, TAPERED LDMOS and ED-MOS able to sustain voltages ranging from 30V to 100V. A highly scalable general high voltage MOSFET model, for the first time, is presented, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, Temperature Coefficient effect and a new general model for drift resistance. Second, the compact modeling of lateral non-uniform doping is presented, which has great impact on the AC behavior. Third, We combined for the first time effects on DC and AC characteristics of LDMOS transistors, with key emphasis on the degradation of transistor capacitances and the influence of the temperature. At our knowledge, our work reported in this work is among the first reports existing in this field. We have essentially shown that the monitoring of capacitance degradation if mandatory for a deep understanding of the degradation mechanisms and, in conjunction with DC parameter degradation, could offer correct insights for reliability issues. Even more, we have shown situations by comparing three fundamental types of parameter degradation method.
    Appears in Collections:[Department of Computer Science and Information Engineering] Theses & dissertations

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