SIMULATION OF NSCR ESD PROTECTION DEVICE FOR BCD 40V TECHNOLOGY

ASIA unversity > 資訊學院 > 資訊工程學系 > 博碩士論文 > Item 310904400/10649

請使用永久網址來引用或連結此文件: http://asiair.asia.edu.tw/ir/handle/310904400/10649

題名:	SIMULATION OF NSCR ESD PROTECTION DEVICE FOR BCD 40V TECHNOLOGY
作者:	Priyono Tri Sulistyanto
貢獻者:	Department of Computer Science and Information Engineering
關鍵詞:	esd nscr bcd p-strap pbl
日期:	2010
上傳時間:	2010-11-04 08:16:16 (UTC+0)
出版者:	Asia University
摘要:	Reliabilities of semiconductor devices become more concerned issues in modern semiconductor integrated circuits. One of failure problems is electro-statics discharge (ESD) failures that caused by triboelectric charging, so to encounter this problem by using ESD protection devices in input-output of integrated circuits. This paper describes about improvement NSCR (N-type Silicon Controlled Rectifier) ESD protection device for 40V BCD (Bipolar CMOS and DMOS) technology comparing between original structure with proposed structures by using process simulation and device simulation. We got lower trigger voltage, higher holding voltage and lower temperature comparing with original structure. P-type Buried Layer (PBL), N-type Buried Layer (NBL) and P+ strap are implemented in order to achieve those results.
顯示於類別:	[資訊工程學系] 博碩士論文

文件中的檔案:

檔案	大小	格式	瀏覽次數
	0Kb	Unknown	338	檢視/開啟

在ASIAIR中所有的資料項目都受到原著作權保護.