A 10-bit current-steering CMOS digital to analog converter

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题名:	A 10-bit current-steering CMOS digital to analog converter
作者:	易昶霈;Yi, Chang-Pei
贡献者:	資訊工程學系
关键词:	AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS Current-steering DAC;Digital to analog converter;DNL;INL;Segmented DAC
日期:	2015-01
上传时间:	2015-03-25 07:43:31 (UTC+0)
摘要:	This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source. The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35 μm 2P4M technology. The power consumption was approximately 7.9 mW at the sample rate of 200 MHz, and the supply voltage was 3.3 V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3 dB under a 1 MHz sine waveform. This work presented a good performance compared with other researches in DNL, INL and power consumption.
關聯:	易昶霈;69(1): 14–17
显示于类别:	[資訊工程學系] 期刊論文

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