An enhanced dual-path ΔΣ analog-to-digital converter

ASIA unversity > 資訊學院 > 資訊工程學系 > 會議論文 > Item 310904400/8821

請使用永久網址來引用或連結此文件: http://asiair.asia.edu.tw/ir/handle/310904400/8821

題名:	An enhanced dual-path ΔΣ analog-to-digital converter
作者:	Nishida, Yoshio;Temes, Gabor C.
貢獻者:	Department of Computer Science and Information Engineering
關鍵詞:	Analog to digital converters;CMOS processs;Delta-sigma ADC;Distortion ratio;Dual path;First-order;Input signal;Quantization noise;Signal bandwidth;Signal to noise;Switched capacitor circuits;Test chips
日期:	2009
上傳時間:	2010-04-08 12:21:58 (UTC+0)
出版者:	Asia University
摘要:	This paper presents an enhanced dual-path delta-sigma ADC. The first-order enhancement of the quantization noise shaping is achieved by employing a switched capacitor circuit technique. A test chip, fabricated in a 0.18-μm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75- dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2<sup>nd</sup> harmonic is -101-dB and the 3<sup>rd</sup> one is -94-dB when a -4.5-dB 100-kHz input signal is applied. ©2009 IEEE.
關聯:	Proceedings - IEEE International Symposium on Circuits and Systems :1333-1336
顯示於類別:	[資訊工程學系] 會議論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
		0Kb	Unknown	325	檢視/開啟
28.doc		30Kb	Microsoft Word	198	檢視/開啟

在ASIAIR中所有的資料項目都受到原著作權保護.