This paper builds an algorithm of determining the BER-minimized
block delay for the joint linear transceiver design with intrablock ZF equalization.
Simulations demonstrate that the proposed optimized ZF transceiver design with
BER-minimized block delay for detection can yield an improved BER performance,
compared with the previous design. Moreover, simulation results show that
a sub-optimum MMSE transceiver design with the proposed BER-minimized
block delay can be devised to perform almost as well as the optimum MMSE
transceiver design.
