Development of SiC Schottky Diode with Linear P-top rings and Optimization of NLD 40V for Higher breakdown voltage and lower On-Resistance

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题名:	Development of SiC Schottky Diode with Linear P-top rings and Optimization of NLD 40V for Higher breakdown voltage and lower On-Resistance
作者:	Mrinal, Aryadeep
贡献者:	資訊工程學系
关键词:	SIC Linear P-top rings planer schottky contact schottky 4H-SiC LDMOS ON-Resistance N-Top
日期:	2014-06-12
上传时间:	2014-09-17 08:38:45 (UTC+0)
出版者:	Asia University
摘要:	In this thesis, a silicon carbide schottky diode with linearly doped p-top ring has been developed and simulated using Silvaco (atlas) TCAD simulator. The comparison of breakdown voltage, forward voltage and electric field has been done for proposed structure i.e. Linear p-top ring structure and planer structure . Also, the effect of different metals as schottky contact, effect of contact length has been discussed. The substrate used in the simulation is 4H-SiC the band gaps of 4H-SiC are approximately three times higher than the one of silicon resulting in a low intrinsic carrier concentration. The band gap also results in an increase in the amount of energy needed by an electron in the valance band in order to make transition to the conduction band. If the energy is large enough, an electron can jump to the conduction band, creation an electron hole pair. However, as the temperature increases, the increase of the intrinsic carrier concentration of SiC is much lower than Silicon due to the wide band gap. Thus, SiC device are a better match for high temperature application. 4H-SiC is the superior of 3C-SiC and 6H-SiC having wider band gap and higher electron mobility. Linear p-top ring structure have a better electric field distribution as the linearly doped p-top suppress the electric field at the edges of the anode contact which also help to increase the reverse breakdown voltage and lower the impact ionization at the edges. The Linear p-top ring has been designed with the linear opening and closing of the p-top mask. Lateral double-diffused metal oxide semiconductor (LDMOS) transistors are widely used in smart power IC designs such as switching power supplies, drivers, amplifiers and automotive applications. To achieve a wide variety of high-voltage applications, LDMOS devices differ in device design significantly. It is very necessary to have a device with lowest On-resistance with best possible breakdown voltage. In the pursuit of getting a structure with best in class on-resistance with acceptable breakdown a NLD 40V structure has been developed with multiple resurf strategy.
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