Nano Imprint Lithography and GaN GAA Nanowire

ASIA unversity > 資訊學院 > 資訊工程學系 > 博碩士論文 > Item 310904400/81037

Please use this identifier to cite or link to this item: http://asiair.asia.edu.tw/ir/handle/310904400/81037

Title:	Nano Imprint Lithography and GaN GAA Nanowire
Authors:	工讀生, 工讀生
Contributors:	資訊工程學系
Keywords:	Nano Imprint Lithography MR-I 7020 NEB 22 A2 GaN Nanowire GAA Nanowire Gate All Around NIL Gallium Nitride FIN Imprint Nano Device TCAD Simulation Nanoimprint Simulation
Date:	2014-05-26
Issue Date:	2014-09-17 08:26:55 (UTC+0)
Publisher:	Asia University
Abstract:	Si master molds are generally patterned by electron-beam lithography (EBL) that is known to be a time consuming nano patterning technique. Thus, developing mold duplication process based on high throughput technique such as nanoimprint lithography can be helpful in reducing its fabrication time and cost. This study aims to develop capabilities in patterning nano structure using thermal nano-imprint lithography. The NEB22 A2, mr- I7000E series negative e-beam resist possess a variety of characteristics desirable for NIL, such as low viscosity, low bulk-volumetric shrinkage, high Young's modulus, high thermal stability, and excellent dry-etch resistance. The excellent oxygen-etch resistance of the barrier material enables a final transfer pattern that is about three times higher than that of the original NIL mold. Based on these imprint on negative photo resist approach is used for pattern transfer into silicon substrates. The result is a high-resolution pattern with feature sizes in the range of nanometer to several microns. We combine Simprint Core simulation software for simulating nanoimprint process and to achieve uniform RLT. Our research results in low RLT as 10-20nm thicknesses for mr-I 7020E photoresist. The simulation results and experimental results are matching. A plot of how RLT across the whole stamp region changes with imprinting duration is shown using simulation. The central, thick line shows the average RLT across the entire stamp; the thin lines indicate the stamp-average RLT plus and minus one standard deviation of the cross-stamp RLT values. Simulated and calibrated for uniform residual layer thickness (RLT) and the cross-sections of RLT are plotted. In cavity filling value of 0 denotes completely empty cavities; a value of 1 in a particular location means that cavities are completely filled in that region. We have achieved completely filled cavities, i.e., value of 1 at all locations. We have achieved RLT around 10nm and even RLT at all location in pattern using mr-I 7020E photoresist imprint. GaN GAA Nanowire: To increase typically low output drive currents from Si Nanowire field-effect transistors (FETs), we show a GaN based GAA Nanowire FET’s effectiveness. The theoretical study is focused on the three dimensional device designs, comparisons, random dopant fluctuation using IFM, and general variability issues including nanowire length, gate work function, and channel thickness are discussed. Performance of GaN GAA Nanowire is found to be increasing as Gate length is increased. Electrical characteristics of FETs including threshold voltage saturation, On/Off current ratio and sub threshold slope (SS) are analysed. GaN GAA structure let to gate control ability improvement compared to Si based Nanowire in electrical performance. The GaN GAA Nanowire subthreshold slope is ~62mV/decade, which is close to the theoretical limit 60 mV/decade and leads to very high Ion/Ioff ratio of 1010-1011. The GaN GAA Nanowire is a very promising candidate for high-performance.
Appears in Collections:	[資訊工程學系] 博碩士論文

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	318	View/Open

View Licence

Loading...