Threshold voltage shift is a major problem for UMOS device. This study explains how device performance can be affected by silicon defects (interstitial and Vacancy). Interstitial may be induced by epitaxy process or trench process. Interstitial enhances the dopant diffusion. In TCAD simulation interstitial distribution is different for different diffusion model and shows shift in the threshold voltage for different interstitial distribution.
Relation:
2014 IEEE 8th International Power Engineering and Optimization Conference ;PEOCO2014), Langkawi, The Jewel of Kedah,
