Process Integration of Best in Class Specific-on Resistance of 20V to 60V 0.18μm Bipolar CMOS DMOS Technology

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題名:	Process Integration of Best in Class Specific-on Resistance of 20V to 60V 0.18μm Bipolar CMOS DMOS Technology
作者:	Yulia, Emita;Hapsari, Emita Yulia;Kumar, Rahul;Kumar, Rahul;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Anil, T.V.;Anil, T.V.
貢獻者:	資訊工程學系
日期:	201310
上傳時間:	2013-11-01 02:18:53 (UTC+0)
摘要:	The evolution of Bipolar CMOS DMOS (BCD) technology leads in the improvement of design technology to produce better device performance with fabrication cost effectiveness as concerned. In this paper, 0.18µm BCD technology with linear p-top layer N-channel LDMOS structure from 20V to 60V is presented with best in class Ron for both N-channel and P-channel LDMOS compared to recent BCD technology works. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.
關聯:	2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
顯示於類別:	[資訊工程學系] 期刊論文

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