"In this work, a novel multiple RESURF P-top rings
LDMOS with shallow trench isolation (STI) stucture based on
the 65 nm baseline low-voltage CMOS technology by threedimentsional Sentaurus process and device simulations. A
optimized uniform electric filed distribution in N-drift region can
be obtained by empolying the multiple P-top rings process
instead of the past proposed gate field plates method in the
extended drain regions. By this way, not only both of high
breakdown voltage exceeded over 40V and low on-resistance
below 20 mΩ-mm2
can be achieved, but also the effect of WNdrift/WSTI ratio on device can be reduce to otain the larger optimal
window of device characteristics, as compared with the
conventional DIELER and graded gate field plate devices. "
