In this work, the behavior of Si-H bond generating interface trap was studied by experiment and TCAD simulation. Its behavior is responsible for the increasing of PMOSFET absolute threshold voltage due to negative bias temperature instability (NBTI) stress for device reliability issue. It was found that the temperature stress has more significant influence on initial interface trap generation as compare to the electric field stress. In addition, fast triangular pulse measurement with elevated temperature was applied to eliminate the NBTI recovery effect and gives a better evaluation of the number of generated interface trap, as compared to the conventional DCIV measurement under NBTI stress.
