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http://asiair.asia.edu.tw/ir/handle/310904400/107141
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| Title: | 600-800V Level Shifter Rectifier & Nanowire Study for Bio-Sensor Application |
| Authors: | AANAND |
| Contributors: | 資訊工程學系 |
| Keywords: | HVIC;LEVEL SHIFTER;INTEGRATED CIRCUIT;FLOATING POLY;HVI;NANO WIRE;BIO SENSOR;DRAIN SATURATION CURRENT;THRESHOLD;VELOCITY INJECTION |
| Date: | 2016 |
| Issue Date: | 2017-03-06 07:14:37 (UTC+0) |
| Publisher: | 亞洲大學 |
| Abstract: | A. High Voltage Integrated Circuits(HVICs)
A new high voltage level up shifter for HVIC is presented that combines the optimized shape of high doping concentration layer (N+ buried layer) and low doping isolation. In order to realize the high voltage level up shifter for HVIC, not only the P- doping level for isolation area but also the shape of N+ buried layer is very important. In P doping level, it is hard to find the optimized condition. If the doping level is higher than proper condition, the breakdown voltage is lower than 600V in the opposite case, there is leakage currents between active to active area. After several experiments, we can find the optimized condition for P-isolation-around 8E12 ion/cm2. Under the optimized P-isolation condition, the shape of N+ buried layer decide the breakdown voltage of level up shifter. For high side gate driver IC, we applied to single p-type isolation technic between high side region and 800V LDMOS (lateral double-diffused MOS) drain to reduce electric potential of junction termination by the crossing drain metal of 800V LDMOS. This single p-type isolation has low doping concentration to be fully depleted for maintaining a high voltage, normally more than 800V. It is limited to remove the cross-talk problem caused by leakage current between high side region and drain of 800V LDMOS in HVIC (High Voltage Integrated Circuits) using self-shielding structure. And a robust high side gate driver IC adapting new self-shielding concept with perfect isolation using Double layer multiple field plate (DLMFP) technology structure is experimentally realized. Experiment results have shown that over 800V breakdown voltage and no leakage current between LDMOS drain and high side region even though the drain voltage of LDMOS is lower than 2V. In addition, highly doped n+ buried layer in the high side region of proposed structure led good dV/dt immunity.
B. Poly silicon nano wire transistors
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention from both the semiconductor industry and academia. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this thesis are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the performance limits and scaling potentials of SNWTs and to address the SNWT design issues. A full three-dimensional, self-consistent, ballistic SNWT simulator has been developed based on the effective-mass approximation with which we have evaluated the upper performance limits of SNWTs with various cross-sections |
| Appears in Collections: | [資訊工程學系] 博碩士論文
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