In the power management applications, the lateral double-diffusion MOS (LDMOS) transistor with high breakdown voltage has long been integrated monolithically in IC process. These power devices are often used as the output driver, and straightly connected to the pin. Without additional Electro Static Discharge (ESD) protection devices, the power devices have to discharge the ESD stress themselves. Because of the ultra high operating voltage, the power dissipation of LDMOS under ESD stress which determined by the discharge current and the holding voltage is extremely high, thus this device is susceptible to burn out. In order to get better ESD robustness, many papers have reported an optimized structure for LDMOS: NLDMOS with an additional P+ in the drain region.
LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor is mainly used in the Ultra high voltage application.
The two major specifications of a LDMOS
Low on-resistance (Ron) and high breakdown voltage.
The major problem for LDMOS is the ESD robustness since the Ndrift is high resistive ,and the current flowline is not directly toward effective to the source contact.
